1. Field of the Invention
The present invention generally relates to the field of semiconductor devices, and more specifically to Fin-based junction diodes.
2. Description of the Related Art
Junction diodes, for example, PIN diodes are commonly used in a wide variety of products such as Radio Frequency (RF) switching devices, telecommunication products, Electrostatic Discharge (ESD) protect devices, imaging sensors, and the like.
The application of PIN diodes may also be extended to photodetectors or optical receivers for emerging optical interconnect technology. For example, when light is illuminated on a PIN photodiode, a current may be generated in the PIN photodiode based on the intensity of the light. When no light is present, the PIN photodiode may be reverse biased, and almost no current may be generated in the PIN photodiode. Therefore, PIN photodiodes are capable of detecting optical signals.
PIN diodes are typically three layer semiconductor devices comprising an intrinsic semiconductor layer sandwiched between p-type and n-type semiconductor layers. Conventional PIN diodes are formed laterally on a substrate by, for example, forming a p-layer, forming an intrinsic (i) layer on top of the p layer, and forming an n layer on top of the i-layer.
However, laterally formed PIN diodes have several disadvantages. In recent years, the need to remain cost and performance competitive in the production of semiconductor devices has resulted in increasing device density in integrated circuits. To facilitate the increase in device density, the feature size of semiconductor devices continues to be reduced. In the case of laterally formed PIN diodes, reducing feature size results in a limited junction area between the p, i, and n layers, thereby reducing the sensitivity of the PIN diode to light, for example.
One solution to achieve reduced feature size without sacrificing PIN diode sensitivity is forming vertical PIN diodes in deep trenches. While forming PIN diodes in deep trenches enhances junction area, and therefore diode sensitivity, the process for forming the PIN diodes is relatively complicated and costly.
Furthermore, the emergence of Fin Field Effect Transistor (FinFET) technology has further complicated the challenge to efficiently form vertical PIN diodes. FinFET based technology allows the formation of high speed CMOS devices. FETs are basic electrical devices used in almost all types on integrated circuit design, for example, in microprocessors, memory, etc. A FinFET comprises a vertical fin shaped structure forming the body of a transistor. Gates may be formed on one or both sides of the fin. A FinFET may provide an increased transistor width, thereby providing the current control of a large transistor without requiring the space consumed by large transistors. However, using FinFET based technology requires the redesign of vertical PIN diodes.
Accordingly, there is a need for developing efficient methods for forming high performance, small feature sized PIN diodes that are compatible with emerging FinFET technology.